Logic device/transceiver/encoder

It can directly drive the common cathode digital tube.

The LCX244 contains eight independent non-inverting buffers with 3-state outputs. The device can be used as a memory address driver, clock driver, and bus-oriented transmitter/receiver. The LCX244 is suitable for low voltage (2.5V or 3.3V) VCC applications and is capable of interfacing to a 5V signal environment. The LCX244 uses an advanced CMOS process to achieve high-speed operation while maintaining the low power consumption of CMOS.

SN74AHC08 Quad 2-Input Positive-AND Gate

The FXMA108 is a configurable plug-in voltage supply converter suitable for unidirectional and bidirectional voltage translation between two logic levels. The device enables voltage translation between as high as 5.5V and as low as 1.65V. The A port tracks the VCCA level and the B port tracks the VCCB level. Bidirectional voltage translation between multiple voltage levels: 1.8V, 2.5V, 3.3V and 5.0V. The device will remain 3-stated until both VCCs reach active levels, allowing either VCC to power up first. If either VCC is removed, an internal power-down control circuit places the device in 3-state. A high level on the /OE input puts both the A side and the B side into a high impedance state, disabling both. The /OE input is provided by VCCA. The FXMA108 supports bidirectional translation and does not require a direction control pin. The device features automatic orientation sensing on both sides. Either port can sense an input signal and pass it on to the other port as an output signal.

SN74LS283 4-Bit Binary Full Adder with Fast Carry

Automotive 4-Channel, 2-Input, 2V to 6V AND Gate 14-SOIC -40 to 125

CD4009UB CMOS Hex Inverting Buffer/Converter

The MC14043B and MC14044B Quad R-S Latch utilizes a monolithic structure constructed using MOS P-channel and N-channel enhancement mode devices. Each latch has an independent Q output as well as set and reset inputs. The Q output is gated through a three-state buffer with a common enable input. These outputs are enabled with a logic '1' or a high level on the enable input; a logic '0' or low level disconnects the latch from the Q output, creating an open circuit at the Q output.