onsemi (Ansemi)

QFN-32(5x5)

Tube

74

The MC100EP195B is a Programmable Delay Chip (PDC) mainly used for clock de-skew and timing adjustment. It provides variable latency for differential NECL/PECL input transitions. The delay section consists of a programmable matrix of gates and multiplexers, as shown in the logic diagram in Figure 2. The EP195B delay increments are digitally selectable with a resolution of approximately 10 ps and a net range of up to 10.2 ns. The desired delay is selected by the value of 10 data select inputs D(9:0), controlled by LEN (pin 10). A low on LEN enables a transparent load mode with real-time latency values ​​determined by D(9:0). A low-high transition on LEN will latch and hold the current value for any subsequent change in D(10:0). Appropriate delay values ​​for various tap numbers associated with D0 (LSB) to D9 (MSB) are shown in Table 6 and Figure 3.