RTC clock synchronization buffer driver delay chip

The MC10EL/100EL15 is a low-skew 1:4 clock distribution chip designed for low-skew clock distribution applications. The device can be driven by differential or single-ended ECL, or by a PECL input signal if a positive supply is used. If a single-ended input is to be used, the VBB output should be connected to the CLK input and bypassed to ground through a 0.01 F capacitor. The VBB output is suitable as a switching reference for the EL15 input in single-ended input conditions, so this pin only sources/sinks 0.5mA. The EL15 has a multiplexed clock input that can be used to distribute lower speed scan or test clocks as well as high speed system clocks. When LOW (or left open and pulled LOW by an input pull-down resistor), the SEL pin selects the differential clock input. The common enable (ENbar) is synchronous, so the output is only enabled/disabled when it is in the low state. This avoids short clock pulses when devices are enabled/disabled, which can happen in asynchronous control. The internal flip-flops are clocked on the falling edge of the input clock, so all relevant specification limits are referenced to the negative edge of the clock input. The 100 series includes temperature compensation.

1:10 LVPECL/HSTL to LVPECL Clock Driver 32-LQFP -40 to 85

The MC100EP195B is a Programmable Delay Chip (PDC) mainly used for clock de-skew and timing adjustment. It provides variable latency for differential NECL/PECL input transitions. The delay section consists of a programmable matrix of gates and multiplexers, as shown in the logic diagram in Figure 2. The EP195B delay increments are digitally selectable with a resolution of approximately 10 ps and a net range of up to 10.2 ns. The desired delay is selected by the value of 10 data select inputs D(9:0), controlled by LEN (pin 10). A low on LEN enables a transparent load mode with real-time latency values ​​determined by D(9:0). A low-high transition on LEN will latch and hold the current value for any subsequent change in D(10:0). Appropriate delay values ​​for various tap numbers associated with D0 (LSB) to D9 (MSB) are shown in Table 6 and Figure 3.