RTC clock synchronization buffer driver delay chip

The MC100LVE111 is a low skew 1:9 dual differential driver designed with clock distribution in mind. The MC100LVE111 is similar in function and performance to the popular MC100E111 with the addition of low voltage operation. It accepts one signal input, which can be differential or single-ended if the VBB output is used. The signal is fanned out to 9 identical differential outputs. The LVE111 has been specifically designed, modeled and produced with low skew as the primary objective. Optimized design and layout help minimize gate-to-gate skew within the device, using empirical modeling to determine process control limits and ensure consistent tpd distribution from lot to lot. A reliable guaranteed low warpage device is thus produced. To ensure compliance with stringent skew specifications, both sides of the differential output are equally terminated to 50W, even if only one side is used. In most applications, all nine differential pairs will be used and therefore terminated. If nine pairs are not required, at least the output pair needs to be terminated on the same side of the package as the pair to be used in order to maintain a minimum skew. Failure to do so will result in a small degradation (in the order of 10-20 ps) of the output propagation delay used, which, while not a big deal for most designs, will mean a loss of skew margin. The MC100LVE111, like most other ECL devices, can operate in PECL mode from a positive VCC supply. Therefore, high-performance clock distribution can be achieved using the LVE111 in +3.3 V systems. Designers can take advantage of the performance of the LVE111 to distribute a low-skew clock on the backside electrode or board. In series or Thevenin lines in a PECL environment, terminations are often used because they do not require an additional power supply. For systems incorporating GTL, parallel termination provides the lowest power