RTC clock synchronization buffer driver delay chip

The MC10EL/100EL15 is a low-skew 1:4 clock distribution chip designed for low-skew clock distribution applications. The device can be driven by differential or single-ended ECL, or by a PECL input signal if a positive supply is used. If a single-ended input is to be used, the VBB output should be connected to the CLK input and bypassed to ground through a 0.01 F capacitor. The VBB output is suitable as a switching reference for the EL15 input in single-ended input conditions, so this pin only sources/sinks 0.5mA. The EL15 has a multiplexed clock input that can be used to distribute lower speed scan or test clocks as well as high speed system clocks. When LOW (or left open and pulled LOW by an input pull-down resistor), the SEL pin selects the differential clock input. The common enable (ENbar) is synchronous, so the output is only enabled/disabled when it is in the low state. This avoids short clock pulses when devices are enabled/disabled, which can happen in asynchronous control. The internal flip-flops are clocked on the falling edge of the input clock, so all relevant specification limits are referenced to the negative edge of the clock input. The 100 series includes temperature compensation.

1-Line to 10-Line Clock Driver 28-SSOP 0 to 70 with I2C Control Interface