RTC clock synchronization buffer driver delay chip

NB3H73113G, part of the OmniClock family, is a one-time programmable (OTP), low-power, PLL-based clock generator that supports any output frequency from 8 kHz to 200 MHz. The device accepts a fundamental mode parallel resonant crystal or a single-ended (LVCMOS/LVTTL) reference clock as input. It generates three single-ended (LVCMOS/LVTTL) outputs, or one single-ended and one differential (LVPECL/LVDS/HCSL/CML) output. These output signals can be modulated using the spread spectrum function of the PLL (Programmable Programmable Spread Spectrum Type, Deviation and Rate) for applications requiring low Electromagnetic Interference (EMI). Individual output enable pins OE[2:0] can be used to enable/disable the output. Individual output voltage pins VDDO[2:0] can be used to individually set the output voltage for each output. The device supports SMBus/I2C interface to SCLK and SDATA. Using standard protocols, data in device registers can be modified to support different configurations. Using PLL bypass mode, a copy of the input clock can be obtained on any or all outputs. The device can be powered down using the power-down pin (PD#). The internal input crystal load capacitance and output drive current provided by the device can be programmed. The device also features an automatic gain control (crystal power limiting) circuit that prevents the device from overdriving an external crystal.