RTC clock synchronization buffer driver delay chip

I2C serial real-time clock chip with 56 bytes RAM, -40℃～+85℃

I2C interface serial clock chip, low operating current: <0.5uA (Max.) @VDD=2.0V

CDCLVC1102 Low Jitter 1:2 LVCMOS Fanout Clock Buffer

Low-jitter, PLL-based frequency multiplier and divider with programmable delay line down to < 10ps 24-SSOP -40 to 85

CDCE925 Programmable 2-PLL VCXO Clock Synthesizer with 2.5-V or 3.3-V LVCMOS Output

IIC interface, low power consumption, working voltage 1.8-2.5V, working temperature -40°C-+85°C, built-in 70-byte register, 32.768HZ square wave output, with charging function and battery voltage measurement function

The MC100LVEP111 is a low-skew 2:1:10 differential driver for clock distribution, accepting two clock sources into one input multiplexer. The PECL input signal can be differential or single-ended (if using the VBB output). The LVEP111 can use HSTL inputs when operating under PECL conditions. The LVEP111 is designed to guarantee low output-to-output skew. Optimized design, layout, and handling minimize skew within and between devices. To ensure the tightest skew, both sides of the differential output are equally terminated to 50Ω, even if only one side is used. If not all ten pairs are used, all output pairs are similarly terminated to the same package side, whether used or not. If no outputs are used on one side, leave these outputs open circuited (unterminated). This keeps output skew to a minimum. Failure to do so will result in a 10-20 ps skew margin loss (propagation delay) in the output being used.

Operating voltage: 2.97V ~ 3.63V