RTC clock synchronization buffer driver delay chip

The MC100EP809 is a low-skew 2:1:9 differential driver designed with clock distribution in mind to combine two clock sources into one input multiplexer. The part is designed for low voltage applications that require a large output to drive a precisely aligned low skew signal to its destination. The two clock inputs are a differential HSTL and a differential LVPECL. Both input pairs can accept LVDS levels. They are selected by the CLK_SEL pin as LVTTL. To avoid runt clock pulses when enabling/disabling the device, the output enable (OE) as LVTTL is synchronous, so it is enabled/disabled only when the output is already in a low state. The MC100EP809 guarantees low output-to-output skew. Optimized design, layout, and handling minimize skew within the device and from device to device. The MC100EP809 output structure uses an open emitter architecture and will be terminated in 50 ohms to ground instead of the standard HSTL configuration. To ensure tight skew specifications are met, both ends of the differential output need to be equally terminated with 50 ohms even if only one output is used. If the output pair is not used, both outputs can be left open (unterminated) without affecting the skew ratio. Designers can take full advantage of the EP809's performance to distribute low-skew clocks across the board's backplane. The HSTL clock input can be driven single-ended by biasing the undriven pin of the input pair.