Memory chip

The CAT24C512C8UTR is a 512-Kb CMOS serial EEPROM internally organized as 65,536 words of 8 bits each. It has a 128-byte page write buffer and supports Standard (100 kHz), Fast (400 kHz), and Fast?Plus (1 MHz) I2C protocols. Write operations can be inhibited by taking the WP pin high (this protects the entire memory). External address pins enable addressing of up to eight CAT24C512C8UTR devices on the same bus. On-chip ECC (Error Correction Code) makes the device suitable for high-reliability applications.