Logic device/transceiver/encoder

6-Channel, 1.65-V to 3.6-V Inverter with Open-Drain Outputs 14-SO -40 to 125

The NB6L611 is a differential 1:2 clock or data fanout buffer. The differential inputs incorporate internal 50 Ω termination resistors accessed through the VTD pin and accept LVPECL, CML, LVDS, LVCMOS, or LVTTL logic levels. The VREFAC pin, the internally generated supply voltage, is provided only for this device. VREFAC is used as the reference voltage for single-ended PECL or NECL inputs. For the single-ended input case, the unused complementary differential input is connected to VREFAC as the switching reference voltage. The VREFAC also couples the capacitor to the input rebias. When used, decouple VREFAC with a 0.01 µF capacitor and limit source/sink current to 0.5 mA. When not in use, the VREFAC output should be left open. The device features a small 3mm x 3 mm 16-pin QFN encapsulation. NB6L611 belongs to the ECLinPS MAX series of high-performance clock and data management products.