Logic device/transceiver/encoder

9-Bit Parity Generator/Checker 14-SOIC -55 to 125

16-Bit Transparent D-Type Latch with 3-State Output 48-TSSOP -40 to 85

NB7V586M is a 1:6 CML clock/data distribution chip with 2:1 clock/data input multiplexer with input select pin. The INx/INxb inputs include internal 50 Ω termination resistors and accept differential LVPECL, CML, or LVDS logic levels. The INx/INxb inputs and core logic are powered by a 1.8 V supply. The NB7V586M generates six identical differential CML output copies of clock or data. The outputs are configured as three sets of two differential pairs. Each bank (or all three banks) can be powered from any combination of 1.8 V or 1.2 V supplies. The 16 mA differential CML output structure provides a matched internal 50 Ω source termination and 400 mV output swing when the external receiver is terminated with 50 Ω to VCCOx. The 1:6 fan-out design is optimized for low output skew and minimal jitter for SONET, GigE, Fiber Channel, backside electrode, and other clock/data distribution applications running typically up to 6 GHz or 10 Gb/s. The VREFAC reference output can be used to rebias capacitor-coupled differential and single-ended input signals. The NB7V586M features a small 5mm x5mm 32-pin QFN lead-free encapsulation.